Microcomputers for debugging that are mounted on a printed board are disclosed in, for example, JP-A-H10-214201 and JP-A-H11-065884. A microcomputer described in JP-A-H10-214201, which eases the development of a program to be stored in an incorporated ROM, comprises a flash memory in which a program under development is stored, and a dedicated input-output terminal for connection to an external ICE. The microcomputer incorporates a debugging circuit having a function of communication with a CPU, a function of communication with the ICE, a trace function, a break function, a function to write program code from the ICE to the flash memory, and a function to send the contents of the flash memory to the ICE.
A microcomputer described in JP-A-H11-065884 comprises a flash ROM, a memory in which a debug program for debugging a program stored to be stored in the flash ROM is stored, and a switching circuit for permitting the CPU to execute the debug program during debugging, thereby enabling debugging without using an in-circuit emulator.
In a target debugging supporting system described in JP-A-2001-306357, an arithmetic and control unit in a target system loads a comparatively simple program for performing communication between an interface for an emulator and a memory into an empty storage area of a working memory of the target system by the emulator, whereby a central processing unit of the target system performs communication with the memory. The interface for the emulator is simplified, and as a result, efficient program modifications can be performed.
A technique as shown in FIG. 4A is used as a software development environment of conventional one-chip microcomputers. According to this technique, a program rewritable memory, e.g., a flash memory 2, is incorporated in a one-chip chip microcomputer 1, and an external device such as an ICE (not shown) controls execution states of a program stored in the flash memory 2 while performing serial communication with the one-chip chip microcomputer 1. In recent years, the number of JTAG devices into which a boundary scan function conforming to IEEE 1149.1 standard (JTAG) is built has been increasing.
Use of this technique only increases the number of IC pins by no more than five pins involved in the addition of the JTAG. However, since the flash memory 2 is constructed to be larger in layout size than a mask ROM, it is difficult to use the same package as a package in which the mask ROM is incorporated at mass production, thus resulting in a problem of package size and terminal pitch being different between stages at software development and at mass production. This problem rarely occurs in the use of a CMOS process with advanced development in minuteness but is serious in an SOI device that employs the trench isolation technology, for example.
Accordingly, as a technique for avoiding such a problem, as shown in FIG. 4B, software development is made using a multichip 3 which encloses a mass-production one-chip microcomputer 4 incorporating a mask ROM 5 and a development chip 6 incorporating a flash memory 7 and a JTAG function in one package. In this case, the mass-production chip 4 is manufactured as an SOI device and the development chip 6 is manufactured as a CMOS device with advanced development in minuteness, whereby the package of the multichip 3 can be sized substantially equally to the mass-production chip 4.
However, because the mass-production chip 4 must perform interchip communication with the development chip 6 incorporating the flash memory 7, the mere multichip construction increases the number of IC terminals to provide the various signal terminals. If serial communication is performed between the chips to avoid this problem, the number of operation cycles may differ in comparison with the case where the mass-production one-chip microcomputer 4 operates alone. Also, limitations in communication may cause the need to reduce program execution speed. Such a problem occurs not only in software development but also in hardware tests on the mass-production chip 4 by use of an IC tester.